After instruction selection, the SelectionDAG structure has nodes representing physical instructions—those directly supported by the processor. The next stage comprises a pre-register allocation scheduler working on SelectionDAG nodes (SDNodes). There are a few different schedulers to choose from and each one of them is a subclass of ScheduleDAGSDNodes (see the file <llvm_source>/ lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp). The scheduler type can be selected in the llc tool by using the -pre-RA-sched=<scheduler> option. The possible values for <scheduler> are the following:
list-ilp,list-hybrid,source, andlist-burr: These options refer to list scheduling algorithms implemented by theScheduleDAGRRListclass (see the file<llvm_source>/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp)fast: TheScheduleDAGFastclass (in<llvm_source>/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp) implements a suboptimal but fast schedulervliw-td: A VLIW-specific...