Vectorization is an important optimization for compilers where we can vectorize code to execute an instruction on multiple datasets in one go. Advance target architecture typically have vector registers set and vector instructions—where broad range of data type (typically 128/246 bit) can be loaded into the vector registers and operations can be performed on those register set, performing two, four, and sometimes eight operations at the same time, with the cost of one scalar operation.
There are two types of vectorization in LLVM—Superword-Level Parallelism (SLP) and loop vectorization. Loop vectorization deals with vectorization opportunities in a loop, while SLP vectorization deals with vectorizing straight-line code in a basic block.
A vector instruction performs Single-instruction multiple-data (SIMD) operations; the same operation on multiple data lanes (in parallel).
Let's look at how SLP Vectorization is implemented in LLVM infrastructure.