The register allocator works on an instruction representation given by the MachineInstr class (MI for short), defined in <llvm_source>/include/llvm/CodeGen/MachineInstr.h. The InstrEmitter pass, which runs after scheduling, transforms SDNode format into MachineInstr format. As the name implies, this representation is closer to the actual target instruction than an IR instruction. Differing from SDNode formats and their DAG form, the MI format is a three-address representation of the program, that is, a sequence of instructions rather than a DAG, which allows the compiler to efficiently represent a specific scheduling decision, that is, the order of each instruction. Each MI holds an opcode number, which is a number that has a meaning only for a specific backend, and a list of operands.
By using the llc option -print-machineinstrs, you can dump machine instructions after all registered passes or after a specific pass by using -print-machineinstrs=<pass-name>...