Book Image

Linux Kernel Programming Part 2 - Char Device Drivers and Kernel Synchronization

By : Kaiwan N Billimoria
Book Image

Linux Kernel Programming Part 2 - Char Device Drivers and Kernel Synchronization

By: Kaiwan N Billimoria

Overview of this book

Linux Kernel Programming Part 2 - Char Device Drivers and Kernel Synchronization is an ideal companion guide to the Linux Kernel Programming book. This book provides a comprehensive introduction for those new to Linux device driver development and will have you up and running with writing misc class character device driver code (on the 5.4 LTS Linux kernel) in next to no time. You'll begin by learning how to write a simple and complete misc class character driver before interfacing your driver with user-mode processes via procfs, sysfs, debugfs, netlink sockets, and ioctl. You'll then find out how to work with hardware I/O memory. The book covers working with hardware interrupts in depth and helps you understand interrupt request (IRQ) allocation, threaded IRQ handlers, tasklets, and softirqs. You'll also explore the practical usage of useful kernel mechanisms, setting up delays, timers, kernel threads, and workqueues. Finally, you'll discover how to deal with the complexity of kernel synchronization with locking technologies (mutexes, spinlocks, and atomic/refcount operators), including more advanced topics such as cache effects, a primer on lock-free techniques, deadlock avoidance (with lockdep), and kernel lock debugging techniques. By the end of this Linux kernel book, you'll have learned the fundamentals of writing Linux character device driver code for real-world projects and products.
Table of Contents (11 chapters)
Section 1: Character Device Driver Basics
User-Kernel Communication Pathways
Handling Hardware Interrupts
Working with Kernel Timers, Threads, and Workqueues
Section 2: Delving Deeper

Understanding and using port-mapped I/O

As we mentioned earlier in the The solution – mapping via I/O memory or I/O port section, besides MMIO, there is another way to perform I/O on peripheral device memory called PMIO, or often simply PIO. It works quite differently from MMIO. Here, the CPU has distinct assembly (and corresponding machine) instructions to enable it to directly read and write I/O memory locations. Not only that, but this I/O memory range is a separate address space altogether, distinct from RAM. These memory locations are called ports. Don't confuse the term port that's being used here with the same term that's used in networking technology; think of this port as an hardware register in that it closely approximates the meaning. (While it's usually 8-bit, peripheral chip registers can actually be of three bit widths: 8, 16, or 32 bits.)

The reality is that most modern processors, even if they do support PMIO...