Book Image

Embedded Systems Architecture - Second Edition

By : Daniele Lacamera
5 (1)
Book Image

Embedded Systems Architecture - Second Edition

5 (1)
By: Daniele Lacamera

Overview of this book

Embedded Systems Architecture begins with a bird’s-eye view of embedded development and how it differs from the other systems that you may be familiar with. This book will help you get the hang of the internal working of various components in real-world systems. You’ll start by setting up a development environment and then move on to the core system architectural concepts, exploring system designs, boot-up mechanisms, and memory management. As you progress through the topics, you’ll explore the programming interface and device drivers to establish communication via TCP/IP and take measures to increase the security of IoT solutions. Finally, you’ll be introduced to multithreaded operating systems through the development of a scheduler and the use of hardware-assisted trusted execution mechanisms. With the help of this book, you will gain the confidence to work with embedded systems at an architectural level and become familiar with various aspects of embedded software development on microcontrollers—such as memory management, multithreading, and RTOS—an approach oriented to memory isolation.
Table of Contents (18 chapters)
1
Part 1 – Introduction to Embedded Systems Development
4
Part 2 – Core System Architecture
8
Part 3 – Device Drivers and Communication Interfaces
13
Part 4 – Multithreading

I2C bus

The third serial communication protocol analyzed in this chapter is I2C. From the communication strategy point of view, this protocol shares some similarities with SPI. However, the default bit rate for I2C communication is much lower, as the protocol privileges lower-power consumption over throughput.

The same two-wire bus can accommodate multiple participants, both masters and slaves, and there is no need for extra signals to physically select the slave of the transaction, as slaves have fixed logic addresses assigned:

Figure 7.6 – I2C bus with three slaves and external pull-up resistors

Figure 7.6 – I2C bus with three slaves and external pull-up resistors

One wire transports the clock generated by the master, and the other is used as a bidirectional synchronous data path. This is possible thanks to the unique mechanism of arbitration of the channel, which relies on the electronic design of the transceivers and may deal with the presence of multiple masters on the same bus in a very clean way.

The...