Book Image

FPGA Programming for Beginners

By : Frank Bruno
5 (1)
Book Image

FPGA Programming for Beginners

5 (1)
By: Frank Bruno

Overview of this book

Field Programmable Gate Arrays (FPGAs) have now become a core part of most modern electronic and computer systems. However, to implement your ideas in the real world, you need to get your head around the FPGA architecture, its toolset, and critical design considerations. FPGA Programming for Beginners will help you bring your ideas to life by guiding you through the entire process of programming FPGAs and designing hardware circuits using SystemVerilog. The book will introduce you to the FPGA and Xilinx architectures and show you how to work on your first project, which includes toggling an LED. You’ll then cover SystemVerilog RTL designs and their implementations. Next, you’ll get to grips with using the combinational Boolean logic design and work on several projects, such as creating a calculator and updating it using FPGA resources. Later, the book will take you through the advanced concepts of AXI and show you how to create a keyboard using PS/2. Finally, you’ll be able to consolidate all the projects in the book to create a unified output using a Video Graphics Array (VGA) controller that you’ll design. By the end of this SystemVerilog FPGA book, you’ll have learned how to work with FPGA systems and be able to design hardware circuits and boards using SystemVerilog programming.
Table of Contents (16 chapters)
1
Section 1: Introduction to FPGAs and Xilinx Architectures
3
Section 2: Introduction to Verilog RTL Design, Simulation, and Implementation
9
Section 3: Interfacing with External Components

Deep dive on synchronization

In project 2, we dipped our toes into synchronizing a signal from an external source. In later designs, we'll be interfacing between multiple clock domains. For instance, in Chapter 5, FPGA Resources and How to Use Them, we'll be interfacing between our main logic and a DDR controller running on a different clock domain.

Why use multiple clocks?

There are several clocking considerations when architecting your FPGA design. Sometimes you are forced to use a given clock for an interface. For example, if you are designing something that interfaces to 10G Ethernet, somewhere in your design will be a multiple of 156.25 MHz or 322.27 MHz depending on if you are interfacing with the PCS or PMA layer. This is because data must be driven out at this frequency and arrives at this frequency.

Other times, you may be looking for high performance or lower power. Increasing your clock speed can increase your throughput or calculations per second if...