As sampling frequency plays such a critical role in determining the quality of the digital representation of the analog signal input, and to avoid aliasing artifacts, it is preferable to use a timer to trigger the conversion rather than to enable continuous conversions as we did in the previous recipe. This recipe,
adcTimerISR_c5v0, illustrates this technique. The aim of this recipe is to configure
TIM2 _CH2 in output compare mode so that it toggles every 100 ms and then use this timing signal to trigger the ADC.
First create a new project called
adcTimerISR.uvprojxand use the RTE manager to configure it as we did for the folder
adcISR_c5v0for the Setting up the ADC recipe.
Custom_ADC.cfrom the previous recipes and add these to the project. Copy
adcISR.cand rename it
adcTimerISR.c. Add this to the project.
main(). Check whether the project successfully builds...