Book Image

LLVM Essentials

By : Mayur Pandey, Suyog Sarda, David Farago
Book Image

LLVM Essentials

By: Mayur Pandey, Suyog Sarda, David Farago

Overview of this book

LLVM is currently the point of interest for many firms, and has a very active open source community. It provides us with a compiler infrastructure that can be used to write a compiler for a language. It provides us with a set of reusable libraries that can be used to optimize code, and a target-independent code generator to generate code for different backends. It also provides us with a lot of other utility tools that can be easily integrated into compiler projects. This book details how you can use the LLVM compiler infrastructure libraries effectively, and will enable you to design your own custom compiler with LLVM in a snap. We start with the basics, where you’ll get to know all about LLVM. We then cover how you can use LLVM library calls to emit intermediate representation (IR) of simple and complex high-level language paradigms. Moving on, we show you how to implement optimizations at different levels, write an optimization pass, generate code that is independent of a target, and then map the code generated to a backend. The book also walks you through CLANG, IR to IR transformations, advanced IR block transformations, and target machines. By the end of this book, you’ll be able to easily utilize the LLVM libraries in your own projects.
Table of Contents (14 chapters)
LLVM Essentials
About the Authors
About the Reviewer

Legalizing SelectionDAG

In the preceding topic, we saw how an IR is converted to SelectionDAG. The whole process didn't involve any knowledge of target architecture for which we are trying to generate code. A DAG node might be illegal for the given target architecture. For example, the X86 architecture doesn't support the sdiv instruction. Instead, it supports sdivrem instruction. This target specific information is conveyed to the SelectionDAG phase by the TargetLowering interface. Targets implement this interface to describe how LLVM IR instructions should be lowered to legal SelectionDAG operations.

In our IR case, we need to 'expand' the sdiv instruction to 'sdivrem' instruction. In the function void SelectionDAGLegalize::LegalizeOp(SDNode *Node), the TargetLowering::Expand case is encountered, which invokes the ExpandNode() function call on that particular node.

void SelectionDAGLegalize::LegalizeOp(SDNode *Node){
case TargetLowering::Expand: