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LLVM Cookbook

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LLVM Cookbook

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LLVM Cookbook
May, 2015 | 296 pages
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Table of Contents (16 chapters)
LLVM Cookbook
LLVM Cookbook
Credits
Credits
About the Authors
About the Authors
About the Reviewers
About the Reviewers
www.PacktPub.com
www.PacktPub.com
Preface
Preface
Free Chapter
1
LLVM Design and Use
LLVM Design and Use
Introduction
Understanding modular design
Cross-compiling Clang/LLVM
Converting a C source code to LLVM assembly
Converting IR to LLVM bitcode
Converting LLVM bitcode to target machine assembly
Converting LLVM bitcode back to LLVM assembly
Transforming LLVM IR
Linking LLVM bitcode
Executing LLVM bitcode
Using the C frontend Clang
Using the GO frontend
Using DragonEgg
2
Steps in Writing a Frontend
Steps in Writing a Frontend
Introduction
Defining a TOY language
Implementing a lexer
Defining Abstract Syntax Tree
Implementing a parser
Parsing simple expressions
Parsing binary expressions
Invoking a driver for parsing
Running lexer and parser on our TOY language
Defining IR code generation methods for each AST class
Generating IR code for expressions
Generating IR code for functions
Adding IR optimization support
3
Extending the Frontend and Adding JIT Support
Extending the Frontend and Adding JIT Support
Introduction
Handling decision making paradigms – if/then/else constructs
Generating code for loops
Handling user-defined operators – binary operators
Handling user-defined operators – unary operators
Adding JIT support
4
Preparing Optimizations
Preparing Optimizations
Introduction
Various levels of optimization
Writing your own LLVM pass
Running your own pass with the opt tool
Using another pass in a new pass
Registering a pass with pass manager
Writing an analysis pass
Writing an alias analysis pass
Using other analysis passes
5
Implementing Optimizations
Implementing Optimizations
Introduction
Writing a dead code elimination pass
Writing an inlining transformation pass
Writing a pass for memory optimization
Combining LLVM IR
Transforming and optimizing loops
Reassociating expressions
Vectorizing IR
Other optimization passes
6
Target-independent Code Generator
Target-independent Code Generator
Introduction
The life of an LLVM IR instruction
Visualizing LLVM IR CFG using GraphViz
Describing targets using TableGen
Defining an instruction set
Adding a machine code descriptor
Implementing the MachineInstrBuilder class
Implementing the MachineBasicBlock class
Implementing the MachineFunction class
Writing an instruction selector
Legalizing SelectionDAG
Optimizing SelectionDAG
Selecting instruction from the DAG
Scheduling instructions in SelectionDAG
7
Optimizing the Machine Code
Optimizing the Machine Code
Introduction
Eliminating common subexpression from machine code
Analyzing live intervals
Allocating registers
Inserting the prologue-epilogue code
Code emission
Tail call optimization
Sibling call optimisation
8
Writing an LLVM Backend
Writing an LLVM Backend
Introduction
Defining registers and registers sets
Defining the calling convention
Defining the instruction set
Implementing frame lowering
Printing an instruction
Selecting an instruction
Adding instruction encoding
Supporting a subtarget
Lowering to multiple instructions
Registering a target
9
Using LLVM for Various Useful Projects
Using LLVM for Various Useful Projects
Introduction
Exception handling in LLVM
Using sanitizers
Writing the garbage collector with LLVM
Converting LLVM IR to JavaScript
Using the Clang Static Analyzer
Using bugpoint
Using LLDB
Using LLVM utility passes
Index
Index

Scheduling instructions in SelectionDAG

So far, we have had SelectionDAG nodes consisting of target-supported instructions and operands. However, the code is still in DAG representation. The target architecture executes instructions in sequential form. So, the next logical step is to schedule the SelectionDAG nodes.

A scheduler assigns the order of execution of instructions from the DAG. In this process, it takes into account various heuristics, such as register pressure, to optimize the execution order of instructions and to minimize latencies in instruction execution. After assigning the order of execution to the DAG nodes, the nodes are converted into a list of MachineInstrs and the SelectionDAG nodes are destroyed.

How to do it…

There are several basic structures that are defined in the ScheduleDAG.h file and implemented in the ScheduleDAG.cpp file. The ScheduleDAG class is a base class for other schedulers to inherit, and it provides only graph-related manipulation operations such as an...

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