These two buses are a fairly common way to interconnect the different devices inside embedded designs. They are not very complicated, and they do not need many wires to operate. Also, their big advantage is easy debugging, as there is only one relatively slow data line, which you can decode easily with just a pen and paper (OK, maybe you do need a bit of additional hardware, such as a logic analyzer), when trying to find the reasons why your bus is not working, or if the data is getting corrupted.
Their disadvantage is perhaps their speed, since they are not too fast. Depending on the protocol and its version, the speeds are at maximum in the Mbps range, usually less. But with low power peripherals, this is often more than enough.
Most of the time the devices using these communication buses have low-level drivers available, so you only need to make the physical connection, configure the bus settings, and implement the necessary data-handling logic.
The Inter-Integrated Circuit (I2C) bus requires only two lines, SCL (serial clock) and SDA (serial data). It has addressing properties, so you can use it to communicate with multiple devices connected to the same bus. The SCL bus is the clock line, and it is used by the master to synchronize the transfers across the bus. The SDA bus is the data line, and this line is operated on by both the master and the slave.
Both of the lines are open-drain designs, so they both require one pull-up resistor, as only the controller can drive the line low.
Note
You can think of an open-drain circuit acting as a switch to the ground, driven with a FET. The circuit can only connect the line to the ground and because of this, we need a pull-up resistor that drives the line high otherwise. The open-collector design creates the same circuit, but the transistor implementing the switch is a BJT.
Only the master initiates the connections, and the slave waits for commands from a master device. Any device can, in theory, be the master; the point is that the master "sets the pace" of the clock line. The operation is performed in the following order:
Start signal generation
Slave address transfer
Data transfer
Stop signal generation
Transferring a single byte looks like this:
When there is no activity on the bus, both the SDA and SCL lines are high (the pull-up resistors) and the master can initiate a new transfer. The transfer is initiated by sending the "start sequence" to the bus. The start sequence (often referred as START or S-bit) is a high-to-low transition of the SDA line while the SCL line is high. This informs all the slave devices to start listening to the next incoming addressing information.
The first byte after the START bit is the addressing information. This is a 7-bit address, followed by the R/W bit. The R/W bit informs the slave whether it is supposed to transmit or receive data. The corresponding slave needs to then respond with the ACK bit.
When the transmission has been agreed upon, the byte-by-byte data transmission takes place. A transferred byte is always acknowledged by the receiver with a 9th ACK bit. If the receiver doesn't acknowledge the byte, the master can generate a STOP event to abort or another START event to retransmit. In case the master does not acknowledge a transmission from the slave, the slave releases the SDA line for the master to decide whether the transmission will be retried.
The Serial Peripheral Interface (SPI) bus is a peripheral bus that, like I2C, can connect multiple devices to each other, and has a one-master-to-multiple-slaves configuration.
This bus is somewhat more advanced than I2C, as it allows full-duplex operation, so that data can be read and transmitted at the same time. It can also operate at a significantly faster speed than I2C, as even a speed of 10 Mbps can be reached between some devices. It does, however, demand for more lines to operate upon, as it needs four wires to function with at least one slave device. Each additional device will need an additional line from the master that serves as slave (chip) select line for that particular device. The master cannot drive the bus in a "broadcast" mode; the specification states that it can only activate one slave at a time. The specified logic signals are:
Sometimes those lines are named slightly differently, but the idea behind them is always the same. There is a line for the clock that defines the transfer speed, separate lines for the transmit and receive operations, and a slave select line to select the receiver of the transmission. Since the data is sent on separate lines, and the addressing takes place with the slave select line, decoding the SPI transmissions is actually easier than it is on I2C, even though you have more lines to watch for.
In general, if you start integrating peripheral devices into your board, we cannot emphasize this enough: a simple USB logic analyzer is invaluable. For example, implementing the SPI transmission between your board and a microcontroller is surprisingly painstaking without the proper tools.
Tip
There are a lot of USB logic analyzers available on the Internet, and all of them are usually good enough to investigate any I2C or SPI issues that you might have during development (you can lower the bus speeds so that even cheaper logic analyzers will be able to decode the transmissions). When selecting a logic analyzer for home use you should select it mainly considering the software quality. We can recommend a product from Saleae, as the software they have created is simple to use and very powerful.