Book Image

Practical Hardware Pentesting, Second edition - Second Edition

By : Jean-Georges Valle
Book Image

Practical Hardware Pentesting, Second edition - Second Edition

By: Jean-Georges Valle

Overview of this book

Practical Hardware Pentesting, Second Edition, is an example-driven guide that will help you plan attacks, hack your embedded devices, and secure the hardware infrastructure. Throughout the book, you’ll explore the functional and security aspects of a device and learn how a system senses and communicates with the outside world. You’ll set up a lab from scratch and gradually work towards an advanced hardware lab. The first part of this book will get you attacking the software of an embedded device. This will get you thinking from an attacker point of view; you’ll understand how devices are attacked, compromised, and how you can harden a device against the most common hardware attack vectors. As you progress, you’ll get to grips with the global architecture of an embedded system and sniff on-board traffic, learn how to identify and formalize threats to the embedded system, and understand its relationship with its ecosystem. This 2nd Edition covers real-world examples featuring various devices like smart TVs, baby monitors, or pacemakers, you’ll discover how to analyze hardware and locate its possible vulnerabilities before going on to explore firmware dumping, analysis, and exploitation. By the end of this book, you’ll and understand how to implement best practices to secure your hardware.
Table of Contents (5 chapters)

Understanding SPI

SPI, or serial-to-parallel interface, is a (usually minimum) three-wire bus. One acts as the clock (CLK), one as Master Out Slave In (MOSI), and one as Master In Slave Out (MISO). If multiple slaves are present in the bus, there is also an additional wire per slave called CS or SS (Chip Select or Slave Select, usually active low).

Here is how multiple slaves are connected:

Figure 6.12 – SPI general architecture

SPI only manages how the bits are transferred on the line; there is no logical layer in the protocol (like I2C has).

On systems where the speed of transfer is important, SPI can come in the QSPI flavor (queued SPI/quad SPI) where there are four data lines. You should note that some chips support both modes and can switch between them with internal commands (that is, commands in the data that are transported by SPI, not commands determined by the SPI protocol itself).

Now that we have seen how the chips are connected, let's see how it works.

Mode...