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Reverse Engineering Armv8-A Systems
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In general, CPU architecture supports exceptions. For example, intel x86, MIPS, Armv7, and RISC-V define exceptions.
When the Arm core generates an exception, it will pause the execution of the software and perform the following actions:
PC) is branched into an exception vector address.We can find assembly instructions at the exception vector address. In practice, these instructions are called exception handlers. At the software level, we can say that when an exception occurs, PC jumps to the exception vector address, and the exception handler runs.
Like other CPU architectures, Armv8-A defines exceptions, including synchronous, IRQ, FIQ, and SError exceptions. These four exceptions can be categorized into two types: synchronous exceptions and asynchronous exceptions. A synchronous exception can be generated while the Arm core...