The STM32F400 evaluation board schematic (http://www.keil.com) shows that a Cirrus Logic CS42L52 codec IC (http://www.cirrus.com) is used, and the I2S bus signals are driven by GPIO port I bits 0, 1, and 3. SDIN and SDOUT are wired together, so the I2S interface must be operated half-duplex. In addition to managing the I2S interface, the microcontroller must also source a Master Clock (MCLK), which clocks the codec's delta-sigma modulators (Note that we described a function to achieve this in Chapter 6, Multimedia Support). A block diagram that summarizes the I2S interface connection is shown, as follows:
The codec also uses MCLK to power an inverter, which supplies a higher DC voltage to support analog parts of the codec. The codec data sheet explains that MCLK should be instantiated and the codec's registers must be configured while the device is powered down and the power up/down sequence outlined in the data sheet must be carefully followed to ensure the codec...