Book Image

Architecting and Building High-Speed SoCs

By : Mounir Maaref
5 (1)
Book Image

Architecting and Building High-Speed SoCs

5 (1)
By: Mounir Maaref

Overview of this book

Modern and complex SoCs can adapt to many demanding system requirements by combining the processing power of ARM processors and the feature-rich Xilinx FPGAs. You’ll need to understand many protocols, use a variety of internal and external interfaces, pinpoint the bottlenecks, and define the architecture of an SoC in an FPGA to produce a superior solution in a timely and cost-efficient manner. This book adopts a practical approach to helping you master both the hardware and software design flows, understand key interconnects and interfaces, analyze the system performance and enhance it using the acceleration techniques, and finally build an RTOS-based software application for an advanced SoC design. You’ll start with an introduction to the FPGA SoCs technology fundamentals and their associated development design tools. Gradually, the book will guide you through building the SoC hardware and software, starting from the architecture definition to testing on a demo board or a virtual platform. The level of complexity evolves as the book progresses and covers advanced applications such as communications, security, and coherent hardware acceleration. By the end of this book, you'll have learned the concepts underlying FPGA SoCs’ advanced features and you’ll have constructed a high-speed SoC targeting a high-end FPGA from the ground up.
Table of Contents (20 chapters)
1
Part 1: Fundamentals and the Main Features of High-Speed SoC and FPGA Designs
7
Part 2: Implementing High-Speed SoC Designs in an FPGA
12
Part 3: Implementation and Integration of Advanced High-Speed FPGA SoCs

Questions

Answer the following questions to test your knowledge of this chapter:

  1. What are the main steps that need to be performed to start building the software for the ETS SoC project?
  2. What are the main options available for XSA file generation? Explain the differences between them.
  3. What needs to be done to generate the boot software for the ETS SoC project when the Vitis project is first created?
  4. What is a domain in the Vitis IDE, what are the steps to create one, and what is it needed for?
  5. What is a BSP and how is it set up in the Vitis IDE?
  6. How can we add a library to a software project in Vitis and what are the build option requirements for it to be recognized?
  7. Propose a data structure format for the ARE that meets the requirements of the microarchitecture of the ETS SoC design.
  8. Is the IPC interrupt from the Cortex-A9 necessary for this system architecture to work?
  9. Suggested another alternative IPC mechanism that avoids the IPC interrupts...