Book Image

Architecting and Building High-Speed SoCs

By : Mounir Maaref
5 (1)
Book Image

Architecting and Building High-Speed SoCs

5 (1)
By: Mounir Maaref

Overview of this book

Modern and complex SoCs can adapt to many demanding system requirements by combining the processing power of ARM processors and the feature-rich Xilinx FPGAs. You’ll need to understand many protocols, use a variety of internal and external interfaces, pinpoint the bottlenecks, and define the architecture of an SoC in an FPGA to produce a superior solution in a timely and cost-efficient manner. This book adopts a practical approach to helping you master both the hardware and software design flows, understand key interconnects and interfaces, analyze the system performance and enhance it using the acceleration techniques, and finally build an RTOS-based software application for an advanced SoC design. You’ll start with an introduction to the FPGA SoCs technology fundamentals and their associated development design tools. Gradually, the book will guide you through building the SoC hardware and software, starting from the architecture definition to testing on a demo board or a virtual platform. The level of complexity evolves as the book progresses and covers advanced applications such as communications, security, and coherent hardware acceleration. By the end of this book, you'll have learned the concepts underlying FPGA SoCs’ advanced features and you’ll have constructed a high-speed SoC targeting a high-end FPGA from the ground up.

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Table of Contents (20 chapters)
Preface
Preface
Who this book is for
What this book covers
To get the most out of this book
Download the example code files
Code in Action
Download the color images
Conventions used
Get in touch
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1
Part 1: Fundamentals and the Main Features of High-Speed SoC and FPGA Designs
Part 1: Fundamentals and the Main Features of High-Speed SoC and FPGA Designs
Free Chapter
2
Chapter 1: Introducing FPGA Devices and SoCs
Chapter 1: Introducing FPGA Devices and SoCs
Xilinx FPGA devices overview
Xilinx SoC overview and history
Xilinx Zynq-7000 SoC family hardware features
Xilinx Zynq Ultrascale+ MPSoC family overview
SoC in ASIC technologies
Summary
Questions
3
Chapter 2: FPGA Devices and SoC Design Tools
Chapter 2: FPGA Devices and SoC Design Tools
Technical requirements
FPGA hardware design flow and tools overview
FPGA SoC hardware design tools
FPGA and SoC hardware verification flow and associated tools
FPGA SoC software design flow and associated tools
Summary
Questions
4
Chapter 3: Basic and Advanced On-Chip Busses and Interconnects
Chapter 3: Basic and Advanced On-Chip Busses and Interconnects
On-chip buses and interconnects overview
ARM AMBA interconnect protocols suite
OCP interconnect protocol
DMA engines and data movements
Data sharing and coherency challenges
Summary
Questions
5
Chapter 4: Connecting High-Speed Devices Using Buses and Interconnects
Chapter 4: Connecting High-Speed Devices Using Buses and Interconnects
Legacy off-chip interconnects overview
Introduction to the PCIe interconnect
Ethernet interconnect
Introduction to the Gen-Z protocol
CCIX protocol and off-chip data coherency
Summary
Questions
6
Chapter 5: Basic and Advanced SoC Interfaces
Chapter 5: Basic and Advanced SoC Interfaces
Interface definition by function
Processor cache fundamentals
Processor MMU fundamentals
Memory and storage interface topology
Summary
Questions
7
Part 2: Implementing High-Speed SoC Designs in an FPGA
Part 2: Implementing High-Speed SoC Designs in an FPGA
8
Chapter 6: What Goes Where in a High-Speed SoC Design
Chapter 6: What Goes Where in a High-Speed SoC Design
The SoC architecture exploration phase
SoC hardware and software partitioning
Hardware and software interfacing and communication
Introducing the Semi-Soft algorithm
Early SoC architecture modeling and the golden model
Summary
Questions
9
Chapter 7: FPGA SoC Hardware Design and Verification Flow
Chapter 7: FPGA SoC Hardware Design and Verification Flow
Technical requirements
Installing the Vivado tools on a Linux VM
Developing the SoC hardware microarchitecture
Design capture of an FPGA SoC hardware subsystem
Understanding the design constraints and PPA
Verifying the FPGA SoC design using RTL simulation
Implementing the FPGA SoC design and FPGA hardware image generation
Summary
Questions
10
Chapter 8: FPGA SoC Software Design Flow
Chapter 8: FPGA SoC Software Design Flow
Technical requirements
Major steps of the SoC software design flow
Setting up the BSP, boot software, drivers, and libraries for the software project
Defining the distributed software microarchitecture for the ETS SoC processors
Building the user software applications to initialize and test the SoC hardware
Summary
Questions
11
Chapter 9: SoC Design Hardware and Software Integration
Chapter 9: SoC Design Hardware and Software Integration
Technical requirements
Connecting to an FPGA SoC board and configuring the FPGA
The emulation platform for running the embedded software
Using QEMU in the Vitis IDE with the ETS SoC project
Using the emulation platform for debugging the SoC test software
Embedded software profiling using the Vitis IDE
Summary
Questions
12
Part 3: Implementation and Integration of Advanced High-Speed FPGA SoCs
Part 3: Implementation and Integration of Advanced High-Speed FPGA SoCs
13
Chapter 10: Building a Complex SoC Hardware Targeting an FPGA
Chapter 10: Building a Complex SoC Hardware Targeting an FPGA
Technical requirements
Building a complex SoC subsystem using Vivado IDE
System performance analysis and the system quantitative studies
Addressing the system coherency and using the Cortex-A9 ACP port
Summary
Questions
14
Chapter 11: Addressing the Security Aspects of an FPGA-Based SoC
Chapter 11: Addressing the Security Aspects of an FPGA-Based SoC
FPGA SoC hardware security features
ARM CPUs and their hardware security paradigm
Software security aspects and how they integrate the hardware’s available features
Building a secure FPGA-based SoC
Summary
Questions
15
Chapter 12: Building a Complex Software with an Embedded Operating System Flow
Chapter 12: Building a Complex Software with an Embedded Operating System Flow
Technical requirements
Embedded OS software design flow for Xilinx FPGA-based SoCs
Customizing and generating the BSP and the bootloader for FreeRTOS
Building a user application and running it on the target
Summary
Questions
16
Chapter 13: Video, Image, and DSP Processing Principles in an FPGA and SoCs
Chapter 13: Video, Image, and DSP Processing Principles in an FPGA and SoCs
DSP techniques using FPGAs
DSP in an SoC and hardware acceleration mechanisms
Video and image processing implementation in FPGA devices and SoCs
Summary
Questions
17
Chapter 14: Communication and Control Systems Implementation in FPGAs and SoCs
Chapter 14: Communication and Control Systems Implementation in FPGAs and SoCs
Communication protocol layers
Communication protocol layers mapping onto FPGA-based SoCs
Control systems overview
Control system hardware and software mappings onto FPGA-based SoCs
Summary
Questions
18
Index
Index
Why subscribe?
19
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Understanding the design constraints and PPA

This section will briefly cover Power, Performance, and Area (PPA) analysis and the physical design constraints required when the SoC RTL is implemented by the tools targeting the FPGA technology.

What is the PPA?

PPA is an analysis we usually perform on a given target IP when designing an SoC for the ASIC technology. This is performed to evaluate its characteristics under these metrics. This analysis provides us with an idea of the IP requirements before the IP is physically implemented in the actual ASIC device. The study helps us in understanding the following:

  • The IP consumption in terms of power, measured in watts. The static power is consumed by simply powering up the IP and the dynamic power when the IP executes the type of workload it is supposed to perform.
  • The maximum clock frequency measured in MHz at which the IP can run, which will give us an idea of whether the IP meets the system requirement in terms of performing...
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