Book Image

Architecting and Building High-Speed SoCs

By : Mounir Maaref
5 (1)
Book Image

Architecting and Building High-Speed SoCs

5 (1)
By: Mounir Maaref

Overview of this book

Modern and complex SoCs can adapt to many demanding system requirements by combining the processing power of ARM processors and the feature-rich Xilinx FPGAs. You’ll need to understand many protocols, use a variety of internal and external interfaces, pinpoint the bottlenecks, and define the architecture of an SoC in an FPGA to produce a superior solution in a timely and cost-efficient manner. This book adopts a practical approach to helping you master both the hardware and software design flows, understand key interconnects and interfaces, analyze the system performance and enhance it using the acceleration techniques, and finally build an RTOS-based software application for an advanced SoC design. You’ll start with an introduction to the FPGA SoCs technology fundamentals and their associated development design tools. Gradually, the book will guide you through building the SoC hardware and software, starting from the architecture definition to testing on a demo board or a virtual platform. The level of complexity evolves as the book progresses and covers advanced applications such as communications, security, and coherent hardware acceleration. By the end of this book, you'll have learned the concepts underlying FPGA SoCs’ advanced features and you’ll have constructed a high-speed SoC targeting a high-end FPGA from the ground up.
Table of Contents (20 chapters)
1
Part 1: Fundamentals and the Main Features of High-Speed SoC and FPGA Designs
7
Part 2: Implementing High-Speed SoC Designs in an FPGA
12
Part 3: Implementation and Integration of Advanced High-Speed FPGA SoCs

Summary

In this chapter, we looked at the key security features that are available in the Zynq-7000 SoC FPGA. We saw that these are threefold: FPGA-specific hardware features, the ARM TrustZone-based framework, and the Secure software execution environment. We covered the secure booting process and how the software and hardware images can be protected using encryption and authentication. Then, we examined how, at boot time, the FPGA features are used to establish the root of trust, decrypt the images, authenticate them, and then load the FSBL and optionally configure the FPGA with the secure bitstream file. We also delved into the Secure and NS software execution worlds and how they interact with each other via a Secure monitor. We examined the ARM TrustZone and the hardware protection mechanism used to make peripherals Secure or NS and how these transactions are qualified at runtime by the AXI and APB bus protocols. We presented a typical Secure system that combines the PS and PL...