Book Image

Architecting and Building High-Speed SoCs

By : Mounir Maaref
5 (1)
Book Image

Architecting and Building High-Speed SoCs

5 (1)
By: Mounir Maaref

Overview of this book

Modern and complex SoCs can adapt to many demanding system requirements by combining the processing power of ARM processors and the feature-rich Xilinx FPGAs. You’ll need to understand many protocols, use a variety of internal and external interfaces, pinpoint the bottlenecks, and define the architecture of an SoC in an FPGA to produce a superior solution in a timely and cost-efficient manner. This book adopts a practical approach to helping you master both the hardware and software design flows, understand key interconnects and interfaces, analyze the system performance and enhance it using the acceleration techniques, and finally build an RTOS-based software application for an advanced SoC design. You’ll start with an introduction to the FPGA SoCs technology fundamentals and their associated development design tools. Gradually, the book will guide you through building the SoC hardware and software, starting from the architecture definition to testing on a demo board or a virtual platform. The level of complexity evolves as the book progresses and covers advanced applications such as communications, security, and coherent hardware acceleration. By the end of this book, you'll have learned the concepts underlying FPGA SoCs’ advanced features and you’ll have constructed a high-speed SoC targeting a high-end FPGA from the ground up.
Table of Contents (20 chapters)
1
Part 1: Fundamentals and the Main Features of High-Speed SoC and FPGA Designs
7
Part 2: Implementing High-Speed SoC Designs in an FPGA
12
Part 3: Implementation and Integration of Advanced High-Speed FPGA SoCs

Questions

Answer the following questions for rest your knowledge of this chapter:

  1. Describe the main features of the SPI bus protocol.
  2. How can the I2C bus protocol interconnect a system with many masters and several slaves?
  3. What are the layers of the PCIe protocol stack?
  4. What are the supported speeds and widths of the PCIe link?
  5. What are the main components in a PCIe RC? How many PCIe RCs can a PCIe system have?
  6. What are the PCIe maximum payload size, maximum read request size, and read completion? What is the relationship between them?
  7. How can the read completion affect the read performance over PCIe at a system level?
  8. Describe how a payload size of 9,000 bytes can be written from DRAM memory in a PCIe end point node, using its DMA engine, into DRAM memory within a PCIe RC node.
  9. What are the main architectural features of the Ethernet protocol?
  10. How can Ethernet interconnect two SoCs and move data between them without using any higher-level...