Book Image

Architecting and Building High-Speed SoCs

By : Mounir Maaref
5 (1)
Book Image

Architecting and Building High-Speed SoCs

5 (1)
By: Mounir Maaref

Overview of this book

Modern and complex SoCs can adapt to many demanding system requirements by combining the processing power of ARM processors and the feature-rich Xilinx FPGAs. You’ll need to understand many protocols, use a variety of internal and external interfaces, pinpoint the bottlenecks, and define the architecture of an SoC in an FPGA to produce a superior solution in a timely and cost-efficient manner. This book adopts a practical approach to helping you master both the hardware and software design flows, understand key interconnects and interfaces, analyze the system performance and enhance it using the acceleration techniques, and finally build an RTOS-based software application for an advanced SoC design. You’ll start with an introduction to the FPGA SoCs technology fundamentals and their associated development design tools. Gradually, the book will guide you through building the SoC hardware and software, starting from the architecture definition to testing on a demo board or a virtual platform. The level of complexity evolves as the book progresses and covers advanced applications such as communications, security, and coherent hardware acceleration. By the end of this book, you'll have learned the concepts underlying FPGA SoCs’ advanced features and you’ll have constructed a high-speed SoC targeting a high-end FPGA from the ground up.
Table of Contents (20 chapters)
1
Part 1: Fundamentals and the Main Features of High-Speed SoC and FPGA Designs
7
Part 2: Implementing High-Speed SoC Designs in an FPGA
12
Part 3: Implementation and Integration of Advanced High-Speed FPGA SoCs

Questions

Answer the following questions to test your knowledge of this chapter:

  1. Describe the TrustZone framework.
  2. List the Zynq-7000 SoC FPGA security-related hardware features.
  3. Where does secure booting start from?
  4. What is an FSBL? How can it be stored externally in a secure way?
  5. Describe the main steps of securely booting a Zynq-7000-based SoC.
  6. What specific control signals are used to implement security in the AMBA specifications?
  7. How is security implemented in the Cortex-A9 processor as far as switching between the Secure execution environment and the NS execution environment?
  8. What is a Secure monitor?
  9. How is the ARM TrustZone hardware protection mechanism implemented in the PL domain?
  10. How could we make the ETS SoC example design in Part 2 of this book more secure?