Book Image

Architecting and Building High-Speed SoCs

By : Mounir Maaref
5 (1)
Book Image

Architecting and Building High-Speed SoCs

5 (1)
By: Mounir Maaref

Overview of this book

Modern and complex SoCs can adapt to many demanding system requirements by combining the processing power of ARM processors and the feature-rich Xilinx FPGAs. You’ll need to understand many protocols, use a variety of internal and external interfaces, pinpoint the bottlenecks, and define the architecture of an SoC in an FPGA to produce a superior solution in a timely and cost-efficient manner. This book adopts a practical approach to helping you master both the hardware and software design flows, understand key interconnects and interfaces, analyze the system performance and enhance it using the acceleration techniques, and finally build an RTOS-based software application for an advanced SoC design. You’ll start with an introduction to the FPGA SoCs technology fundamentals and their associated development design tools. Gradually, the book will guide you through building the SoC hardware and software, starting from the architecture definition to testing on a demo board or a virtual platform. The level of complexity evolves as the book progresses and covers advanced applications such as communications, security, and coherent hardware acceleration. By the end of this book, you'll have learned the concepts underlying FPGA SoCs’ advanced features and you’ll have constructed a high-speed SoC targeting a high-end FPGA from the ground up.
Table of Contents (20 chapters)
1
Part 1: Fundamentals and the Main Features of High-Speed SoC and FPGA Designs
7
Part 2: Implementing High-Speed SoC Designs in an FPGA
12
Part 3: Implementation and Integration of Advanced High-Speed FPGA SoCs

Index

As this ebook edition doesn't have fixed pagination, the page numbers below are hyperlinked for reference only, based on the printed edition of this book.

A

Acceleration Request Entry (ARE) 188, 265

Acceleration Request Queue (ARQ) 188

Acceleration Requests (ARE) 317

Accelerator Coherency Port (ACP) 312

accelerators port

used, for extending cache coherency at SoC level 88, 89

Accellera SystemC

used, for system modeling 171, 172

ACE-4

used, for extending cache coherency at SoC level 89

ACE bus protocol

cache line states, rules 73

characteristics 71-73

evolution 71

interface signals 74, 75

overview 71

supported transactions 76, 77

system implementation, example 77

Advanced Encryption Standards (AES) 328

Advanced Host Controller Interface (AHCI) 23

Advanced Peripheral Bus (APB) 52

Advanced System Bus (ASB) 52

Advance High-performance Bus (AHB) 52

Advance Microcontroller Bus Architecture...