Book Image

Modern Computer Architecture and Organization

By : Jim Ledin
Book Image

Modern Computer Architecture and Organization

By: Jim Ledin

Overview of this book

Are you a software developer, systems designer, or computer architecture student looking for a methodical introduction to digital device architectures but overwhelmed by their complexity? This book will help you to learn how modern computer systems work, from the lowest level of transistor switching to the macro view of collaborating multiprocessor servers. You'll gain unique insights into the internal behavior of processors that execute the code developed in high-level languages and enable you to design more efficient and scalable software systems. The book will teach you the fundamentals of computer systems including transistors, logic gates, sequential logic, and instruction operations. You will learn details of modern processor architectures and instruction sets including x86, x64, ARM, and RISC-V. You will see how to implement a RISC-V processor in a low-cost FPGA board and how to write a quantum computing program and run it on an actual quantum computer. By the end of this book, you will have a thorough understanding of modern processor and computer architectures and the future directions these architectures are likely to take.

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Table of Contents (20 chapters)
Preface
Preface
Who this book is for
What this book covers
To get the most out of this book
Code in Action
Conventions used
Get in touch
Reviews
1
Section 1: Fundamentals of Computer Architecture
Section 1: Fundamentals of Computer Architecture
Free Chapter
2
Chapter 1: Introducing Computer Architecture
Chapter 1: Introducing Computer Architecture
The evolution of automated computing devices
Moore's law
Computer architecture
Summary
Exercises
3
Chapter 2: Digital Logic
Chapter 2: Digital Logic
Electrical circuits
The transistor
Logic gates
Latches
Flip-flops
Registers
Adders
Clocking
Sequential logic
Hardware description languages
Summary
Exercises
4
Chapter 3: Processor Elements
Chapter 3: Processor Elements
A simple processor
The instruction set
Addressing modes
Instruction categories
Interrupt processing
Input/output operations
Summary
Exercises
5
Chapter 4: Computer System Components
Chapter 4: Computer System Components
Technical requirements
Memory subsystem
Introducing the MOSFET
Constructing DRAM circuits with MOSFETs
I/O subsystem
Graphics displays
Network interface
Keyboard and mouse
Modern computer system specifications
Summary
Exercises
6
Chapter 5: Hardware-Software Interface
Chapter 5: Hardware-Software Interface
Device drivers
BIOS
The boot process
Operating systems
Processes and threads
Multiprocessing
Summary
Exercises
7
Chapter 6: Specialized Computing Domains
Chapter 6: Specialized Computing Domains
Real-time computing
Digital signal processing
GPU processing
Examples of specialized architectures
Summary
Exercises
8
Section 2: Processor Architectures and Instruction Sets
Section 2: Processor Architectures and Instruction Sets
9
Chapter 7: Processor and Memory Architectures
Chapter 7: Processor and Memory Architectures
Technical Requirements
The von Neumann, Harvard, and modified Harvard architectures
Physical and virtual memory
Paged virtual memory
Memory management unit
Summary
Exercises
10
Chapter 8: Performance-Enhancing Techniques
Chapter 8: Performance-Enhancing Techniques
Cache memory
Instruction pipelining
Simultaneous multithreading
SIMD processing
Summary
Exercises
11
Chapter 9: Specialized Processor Extensions
Chapter 9: Specialized Processor Extensions
Technical requirements
Privileged processor modes
Floating-point mathematics
Power management
System security management
Summary
Exercises
12
Chapter 10: Modern Processor Architectures and Instruction Sets
Chapter 10: Modern Processor Architectures and Instruction Sets
Technical requirements
x86 architecture and instruction set
x64 architecture and instruction set
32-bit ARM architecture and instruction set
64-bit ARM architecture and instruction set
Summary
Exercises
13
Chapter 11: The RISC-V Architecture and Instruction Set
Chapter 11: The RISC-V Architecture and Instruction Set
Technical requirements
The RISC-V architecture and features
The RISC-V base instruction set
RISC-V extensions
64-bit RISC-V
Standard RISC-V configurations
RISC-V assembly language
Implementing RISC-V in an FPGA
Summary
Exercises
14
Section 3: Applications of Computer Architecture
Section 3: Applications of Computer Architecture
15
Chapter 12: Processor Virtualization
Chapter 12: Processor Virtualization
Technical requirements
Introducing virtualization
Virtualization challenges
Virtualizing modern processors
Virtualization tools
Virtualization and cloud computing
Summary
Exercises
16
Chapter 13: Domain-Specific Computer Architectures
Chapter 13: Domain-Specific Computer Architectures
Technical requirements
Architecting computer systems to meet unique requirements
Smartphone architecture
Personal computer architecture
Warehouse-scale computing architecture
Neural networks and machine learning architectures
Summary
Exercises
17
Chapter 14: Future Directions in Computer Architectures
Chapter 14: Future Directions in Computer Architectures
The ongoing evolution of computer architectures
Extrapolating from current trends
Potentially disruptive technologies
Building a future-tolerant skill set
Summary
Exercises
18
Answers to Exercises
Exercise 1
Answer
Exercise 2
Exercise 3
Answer
Exercise 4
Answer
Exercise 5
Answer
Exercise 6
Answer
Exercise 1
Answer
Exercise 2
Answer
Exercise 3
Answer
Answer
Exercise 5
Answer
Exercise 6
Exercise 1
Answer
Exercise 2
Answer
Exercise 3
Answer
Exercise 4
Answer
Exercise 5
Answer
Exercise 6
Answer
Exercise 1
Answer
Exercise 2
Answer
Exercise 1
Answer
Exercise 2
Answer
Exercise 1
Answer
Exercise 2
Answer
Exercise 3
Answer
Exercise 1
Answer
Exercise 2
Answer
Exercise 3
Answer
Exercise 1
Answer
Exercise 2
Answer
Exercise 3
Answer
Exercise 1
Answer
Exercise 2
Answer
Exercise 3
Answer
Exercise 4
Answer
Exercise 5
Answer
Exercise 6
Answer
Exercise 7
Answer
Exercise 8
Answer
Exercise 1
Answer
Exercise 2
Answer
Exercise 3
Answer
Exercise 4
Answer
Exercise 5
Answer
Exercise 6
Answer
Exercise 8
Answer
Exercise 1
Answer
Exercise 2
Answer
Exercise 3
Answer
Exercise 4
Answer
Exercise 1
Answer
Exercise 2
Answer
Exercise 3
Answer
Exercise 1
Answer
Exercise 2
Answer
Answer
Exercise 2
Answer
Exercise 3
Answer
Exercise 4
Answer
19
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The von Neumann, Harvard, and modified Harvard architectures

In earlier chapters, we touched briefly on the history and modern applications of the von Neumann, Harvard, and modified Harvard processor architectures. In this section, we'll examine each of these configurations in greater detail and look at the types of computing applications where each of these architectures tends to be applied.

The von Neumann architecture

The von Neumann architecture was introduced by John von Neumann in 1945. This processor configuration consists of a control unit, an arithmetic logic unit, a register set, and a memory region containing program instructions and data. The key feature distinguishing the von Neumann architecture from the Harvard architecture is the use of a single area of memory for program instructions and the data acted upon by those instructions. It is conceptually straightforward for programmers, and relatively easier for circuit designers, to locate all of the code and...

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