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Table Of Contents
LLVM Code Generation
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In this chapter, you learned how the Machine pass pipeline is structured and the implications of this structure on the IR. You saw that you start from the Machine IR in SSA form with virtual registers, then go to the non-SSA form but still with virtual registers, and finish with pure physical registers before transitioning to the MC layer.
Next, you learned how to inject passes into the Machine pass pipeline at various places using the TargetPassConfig class. You also learned how to examine the existing passes of the CodeGen passes to see what they need to perform their job.
Finally, you learned about three passes that the CodeGen library offers – CodeGenPrepare, PeepholeOptimizer, and MachineCombiner – and got a taste of what you need to do to use these passes to their full potential.
In the next chapter, we’ll focus on one of the mandatory steps of the Machine pass pipeline: the instruction selection step.