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Table Of Contents
LLVM Code Generation
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Now that you have completed reading this chapter, try answering the following questions to test your knowledge:
No, the register allocation infrastructure consists of several passes that work together to perform the register allocation. In an optimized pass pipeline, you can count at least three passes: the coalescer, the allocator, and the virtual register rewriter.
More details are in the Overview of register allocation in LLVM section.
The two analysis passes are the SlotIndexes and LiveIntervals passes, as explained in the Overview of register allocation in LLVM section.
Your target needs to implement the hooks that allow the insertion of spilled code.
See the Enabling the register...