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LLVM Code Generation

LLVM Code Generation

By : Quentin Colombet
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LLVM Code Generation

LLVM Code Generation

1 (1)
By: Quentin Colombet

Overview of this book

The LLVM infrastructure is a popular compiler ecosystem widely used in the tech industry and academia. This technology is crucial for both experienced and aspiring compiler developers looking to make an impact in the field. Written by Quentin Colombet, a veteran LLVM contributor and architect of the GlobalISel framework, this book provides a primer on the main aspects of LLVM, with an emphasis on its backend infrastructure; that is, everything needed to transform the intermediate representation (IR) produced by frontends like Clang into assembly code and object files. You’ll learn how to write an optimizing code generator for a toy backend in LLVM. The chapters will guide you step by step through building this backend while exploring key concepts, such as the ABI, cost model, and register allocation. You’ll also find out how to express these concepts using LLVM's existing infrastructure and how established backends address these challenges. Furthermore, the book features code snippets that demonstrate the actual APIs. By the end of this book, you’ll have gained a deeper understanding of LLVM. The concepts presented are expected to remain stable across different LLVM versions, making this book a reliable quick reference guide for understanding LLVM.
Table of Contents (30 chapters)
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Part 1: Getting Started with LLVM
8
Part 2: Middle-End: LLVM IR to LLVM IR
13
Part 3: Introduction to the Backend
17
Part 4: LLVM IR to Machine IR
22
Part 5: Final Lowering and Optimizations
28
Other Books You May Enjoy
29
Index

The scheduling model

In the LLVM scheduling infrastructure, the scheduling model is the piece that holds all the information about the resources of the subtarget and how they are used by the various instructions.

Note

We always speak about subtargets when talking about scheduling capabilities. This is because the scheduling capabilities are tied to the microarchitecture of your target, hence its subtarget. For instance, the scheduling capabilities of the x86 target are different for the Haswell and the Sapphire Rapids microarchitectures.

This information is described statically with TableGen and then used by the scheduling infrastructure to make decisions.

In typical LLVM fashion, there are two complementary ways to describe your scheduling model. At the core, both methods model how processor resources are used, such as the arithmetic logic unit (ALU) and load-store unit, but to simplify it, one does that in terms of scheduling events and the other in...

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LLVM Code Generation
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