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Table Of Contents
LLVM Code Generation
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Now that you have completed reading this chapter, try answering the following questions to test your knowledge:
The DDG represents all the scheduling constraints of the instructions in a scheduling region. Put differently, it represents the weak order in which the instructions must appear in the linearized sequence of instructions.
See the Overview of the instruction scheduling framework section for more information.
The concept of mutations allows you to tweak the dependencies of the DDG after it is fully constructed for the current scheduling region. Thanks to this construct, you can, for instance, over-constrain the DDG to limit the freedom that the scheduler has around certain instructions.
Refer to the The ScheduleDAGInstrs class section for more details.