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Table Of Contents
LLVM Code Generation
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The instruction selection phase of the whole instruction selection pipeline is comparatively easier than anything you have done so far. Additionally, the LLVM infrastructure provides a DSL to describe the selection patterns. This DSL, in TableGen, allows us to reuse a lot of the instruction selection description between all three selectors, although, for FastISel, the supported patterns are limited. Obviously, not everything is as easy as writing a few patterns in TableGen, but we will go into these considerations in due time. First, let us introduce how you describe your selection patterns in TableGen.
If you look at the Instruction TableGen class, you will notice that it features a Pattern field. This field is one of the ways you can describe a selection pattern for a particular instruction. The second way to describe a pattern is by instantiating a record of the Pat class. In both cases, you describe a dag instance...