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  • Book Overview & Buying LLVM Code Generation
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LLVM Code Generation

LLVM Code Generation

By : Quentin Colombet
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LLVM Code Generation

LLVM Code Generation

1 (1)
By: Quentin Colombet

Overview of this book

The LLVM infrastructure is a popular compiler ecosystem widely used in the tech industry and academia. This technology is crucial for both experienced and aspiring compiler developers looking to make an impact in the field. Written by Quentin Colombet, a veteran LLVM contributor and architect of the GlobalISel framework, this book provides a primer on the main aspects of LLVM, with an emphasis on its backend infrastructure; that is, everything needed to transform the intermediate representation (IR) produced by frontends like Clang into assembly code and object files. You’ll learn how to write an optimizing code generator for a toy backend in LLVM. The chapters will guide you step by step through building this backend while exploring key concepts, such as the ABI, cost model, and register allocation. You’ll also find out how to express these concepts using LLVM's existing infrastructure and how established backends address these challenges. Furthermore, the book features code snippets that demonstrate the actual APIs. By the end of this book, you’ll have gained a deeper understanding of LLVM. The concepts presented are expected to remain stable across different LLVM versions, making this book a reliable quick reference guide for understanding LLVM.
Table of Contents (30 chapters)
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Part 1: Getting Started with LLVM
8
Part 2: Middle-End: LLVM IR to LLVM IR
13
Part 3: Introduction to the Backend
17
Part 4: LLVM IR to Machine IR
22
Part 5: Final Lowering and Optimizations
28
Other Books You May Enjoy
29
Index

Overview of register allocation in LLVM

In LLVM, register allocation is split into two main optimization passes in the machine pass pipeline. More specifically, after eliminating the static single assignment (SSA) form of the input program during the PHI-elimination pass, as you learned in Chapter 13, LLVM performs the register coalescing phase and, later, the register assignment phase. The coalescing phase consists of merging variables connected by a COPY instruction together. The assignment phase consists of replacing the virtual registers with physical registers or memory locations. Figure 19.1 illustrates these two phases, while Figure 19.2 illustrates the register allocation process in LLVM:

Figure 19.1: The role of the register coalescing and register assignment phases

Figure 19.1: The role of the register coalescing and register assignment phases

Figure 19.1 demonstrates how the register coalescing phase simplifies the Machine intermediate representation (IR) by merging the %v1 and %v2 variables. Thanks to this coalescing, the COPY instruction...

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LLVM Code Generation
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