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Table Of Contents
Modern Computer Architecture and Organization - Third Edition
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The GA102 has 12 memory controllers that interface with GDDR6X memory. The RTX 3090 has 24 GDDR6X memory modules, each with a capacity of 1 GB. Each module provides a 16-bit interface to its memory controller, with 2 independent chips serving each controller. The result is 32 bits of parallel communication per memory controller and 384 bits of parallel data transfer across the 12 controllers. Twelve memory modules are installed on each side of the GPU circuit board.
Internally, memory operations are clocked at 1.219 GHz. Communication with the system processor occurs at a 4x higher clock rate, and transfers are double data rate, meaning a new transfer occurs on each clock edge. GDDR6X utilizes PAM4 signaling, as discussed in Chapter 4, Computer System Components, which transfers two bits per clock edge on each pin. The bit rate when reading or writing memory is therefore 1.219x109 x 2 x 2 x 4 = 19.5 Gb/s per pin. With a total of 384 parallel bits, the memory throughput...