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Book Overview & Buying
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Table Of Contents
Modern Computer Architecture and Organization - Third Edition
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Processor architectures supporting paged virtual memory either implement the memory management unit (MMU) functionality within the processor itself or, in older designs, as a separate integrated circuit. Within the MMU, the processor's virtual address space is divided into page-sized allocation units.
Pages may be of a fixed size, as in the Windows NT example discussed earlier, or an MMU may support multiple sizes. Modern processors, including later-generation x86 processors, often support two page sizes, one small and one large. Small pages are typically a few KB, while a large page may be a few MB. Support for large pages avoids the inefficiencies associated with allocating numerous smaller pages when working with multi-megabyte data objects.
As discussed in the previous section, the MMU typically includes a cache to enhance memory access speed by eliminating the need to traverse the page table directory and perform page table lookup for each memory access...